Joint Test Action Group (JTAG) testing is ubiquitous in today's circuit board manufacturing environment. However, current testing protocols do have their drawbacks. Typical problems in this area include increased test time, which is typically due to handling products when performing JTAG/programming and/or system tests of printed circuit boards (PCB) used in “hot insertion” systems.
Performing the JTAG/programming in the system creates three clear problems. The first problem is the failure of a unit under test (UUT), which is done by the management complex unit (MCU) due to inserting the un-programmed PCB in the system. The second problem is the interference by the management complex trying to access the UUT while performing JTAG testing. The third problem is the initialization of the PCB after programming without removing and reinstalling the UUT, or the power down of the entire system causing an extended reboot cycle.
Thus, a method is needed to address these problems (and others): not only in the JTAG environment, but also in other testing environments in which timing constraints are critical. The ability to properly resolve these significant testing issues creates an interesting challenge for programmers, software engineers, and manufacturers alike.